A process variation aware system-level framework to model on-chip communication system in support of fault tolerant analysis
On-chip interconnect communication system consists of the drivers, interconnect wires and receivers. Several on-chip communication system models have been developed for the purpose of on-chip fault-tolerant communication research. While most of these models improved the channel modeling, the effects...
Saved in:
Main Authors: | , , , |
---|---|
Format: | Conference or Workshop Item |
Language: | English |
Published: |
IEEE
2009
|
Online Access: | http://psasir.upm.edu.my/id/eprint/68595/1/A%20process%20variation%20aware%20system-level%20framework%20to%20model%20on-chip%20communication%20system%20in%20support%20of%20fault%20tolerant%20analysis.pdf http://psasir.upm.edu.my/id/eprint/68595/ |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Universiti Putra Malaysia |
Language: | English |