A process variation aware system-level framework to model on-chip communication system in support of fault tolerant analysis
On-chip interconnect communication system consists of the drivers, interconnect wires and receivers. Several on-chip communication system models have been developed for the purpose of on-chip fault-tolerant communication research. While most of these models improved the channel modeling, the effects...
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| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2009
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| Online Access: | http://psasir.upm.edu.my/id/eprint/68595/1/A%20process%20variation%20aware%20system-level%20framework%20to%20model%20on-chip%20communication%20system%20in%20support%20of%20fault%20tolerant%20analysis.pdf http://psasir.upm.edu.my/id/eprint/68595/ |
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| Institution: | Universiti Putra Malaysia |
| Language: | English |
| Summary: | On-chip interconnect communication system consists of the drivers, interconnect wires and receivers. Several on-chip communication system models have been developed for the purpose of on-chip fault-tolerant communication research. While most of these models improved the channel modeling, the effects of the drivers and receivers to the whole communication system were largely ignored. In this paper, we introduce a comprehensive, system-level framework, to capture and integrate the characteristics of the channel as well as the drivers and receivers. The proposed framework offers a methodology to model the on-chip interconnect communication system and can provide a flexible and updateable platform to evaluate fault-tolerant communication approaches. Furthermore, the current deterministic paradigm which end is worst case analysis pessimism is avoided by shifting towards statistical design flow to reduce uncertainties caused by process variation. |
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