Optimization Of Process Parameter Variation In Double-Gate FinFET Model On Electrical Characteristics Using Statistical Method For Reduced Variability And Enhanced Performance

• Main Authors: Salehuddin, Fauziyah, Mohd Zain, Anis Suhaila, Haroon, Hazura, Abdul Razak, Hanim, Idris@Othman, Siti Khadijah, Ahmadi, Ibrahim
• Format: Technical Report
• Language: English
• Published: UTeM 2020
• Online Access: http://eprints.utem.edu.my/id/eprint/25464/1/Optimization%20Of%20Process%20Parameter%20Variation%20In%20Double-Gate%20Finfet%20Model%20On%20Electrical%20Characteristics%20Using%20Statistical%20Method%20For%20Reduced%20Variability%20And%20Enhanced%20Performance.pdf; http://eprints.utem.edu.my/id/eprint/25464/; https://plh.utem.edu.my/cgi-bin/koha/opac-detail.pl?biblionumber=118114
• Institution: Universiti Teknikal Malaysia Melaka

The conventional transistor device has been effective to provide for continual improvements in integrated circuit performance and cost per function with every technology node. However, transistor scaling has become increasingly difficult in the sub-45 nm regime. The main challenges for continued scaling of bulk-Si CMOS technology are the increment leakage current and variability in transistor performance. Since Moore’s law driven scaling of planar MOSFET faces formidable challenges in the nanometer regime, the multi-gate MOSFET devices have emerged as their successors. Owing to the presence of multiple-gate such as Double Gate FinFETs (DG-FinFETs) are able to tackle short-channel effects better than conventional planar MOSFETs at deeply scaled technology nodes and thus enable continued transistor scaling. In here, the traditional polysilicon/SiO2 material was replaced by the metal gate/high-k dielectrics in order to increase the drive current for meeting the requirement of high performance multigate technology. In this research, the ATHENA and ATLAS module of SILVACO software were used to simulate the virtual fabrication and the electrical performance of the device. There are several process parameters that will be investigated. The data from the simulation was used to determine the dominance of the process parameter effects on the device’s characteristics. The optimization of the process parameter variations towards the multiple device’s characteristics of DG-FinFETs were done by utilizing appropriate statistical modelling to meet the requirement of low power multi-gate technology for the year 2020 as predicted by International Technology Roadmap Semiconductor (ITRS) 2013. Statistical modelling such as Taguchi method and RSM were assist designers to optimize the process parameters of the device.