130 nm low power CMOS analog multiplier

• Main Authors: Abu Naim, Ahmad Safuan, Ruslan, Siti Hawa
• Format: Article
• Language: English
• Published: IOP Publishing 2018
• Subjects: TK5101-6720 Telecommunication. Including telegraphy, telephone, radio, radar, television
• Online Access: http://eprints.uthm.edu.my/2901/1/AJ%202019%20%2864%29.pdf; http://eprints.uthm.edu.my/2901/; https://iopscience.iop.org/article/10.1088/1742-6596/1049/1/012071
• Institution: Universiti Tun Hussein Onn Malaysia

Processing analog signal often involves analog multiplier and the multiplier is part of system on chip (SoC). Designing such system with a low power consumption is crucial nowadays. It is very important to increase the system battery lifetime. The design also must be smaller in size. In order to reduce the power consumption of the multiplier, an architecture that require smaller current must be designed and the approach is to use a design that is able to function at a low voltage supply. This project has designed the analog multiplier with a low power consumption using Silterra 130 nm Complementary Metal Oxide Semiconductor (CMOS) technology. A four quadrant technique is applied in the design. The scaling of transistor will help in reducing the size of the analog multiplier, and the proposed circuit architecture has produced a compact multiplier. Cadence electronic design automation (EDA) Tools is used to design the circuit. The schematic, layout, physical verification and parasitic extraction with post layout simulation are done to verify the multiplier circuit is functioning. The analog multiplier is operated with 1.2 V voltage supply and the power consumption is 98 μW. At 1 V, the power consumption is 32 μW. The total area for the design is 99 μm².