Design and analysis of electrical characteristics of 14nm SOI-based trigate gaussian channel junctionless FinFET
Planar MOSFETs are reaching their physical limits. To overcome the limitations and improve channel gate control, FinFET technology, which uses many gate devices, is a superior choice while lowering the size of planar MOSFETs even further. In this paper, 14nm Silicon-On-Insulator-based Trigate Gaussi...
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my.utm.1078882024-10-08T06:53:41Z http://eprints.utm.my/107888/ Design and analysis of electrical characteristics of 14nm SOI-based trigate gaussian channel junctionless FinFET Ramakrishnan, Mathangi Alias, Nurul Ezaila Hamzah, Afiq Tan, Michael Loong Peng Yusof, Yusmeeraz Natarajamoorthy, Mathan TK Electrical engineering. Electronics Nuclear engineering Planar MOSFETs are reaching their physical limits. To overcome the limitations and improve channel gate control, FinFET technology, which uses many gate devices, is a superior choice while lowering the size of planar MOSFETs even further. In this paper, 14nm Silicon-On-Insulator-based Trigate Gaussian Channel Junctionless FinFET is presented. The gate length of 14nm is considered along with an Equivalent Oxide Thickness of 1nm, 5nm as fin width, and the work function of the gate metal is 4.75eV. The device architecture has a non-uniform doping profile (Gaussian distribution) across the fin’s thickness. It is devised to address the effects of Random Dopant Fluctuations such as channel mobility degradation in Junctionless FinFET based devices. The impact of fin height (Fh), gate dielectric and spacer dielectric on the Drain Induced Barrier Lowering, Subthreshold Swing, drain current of GC-JLFinFET is analyzed. The results show that the Ion=101.5µA/µm and Ion/Ioff is 3.2x107 are obtained for the proposed device structure compared to the existing structure, which has Ion/Ioff of 1.1x107. Furthermore, the proposed design shows better efficiency in short channel characteristics, namely DIBL=25.3 mV/V, Subthreshold Swing=63.88 mV/dec and Transconductance =3.621x105 S/µm. Thus the Gaussian Channel-based FinFET architecture can provide optimum results for Junctionless-based FinFET devices. 2023 Conference or Workshop Item PeerReviewed application/pdf en http://eprints.utm.my/107888/1/NurulEzailaAlias2023_DesignandAnalysisofElectricalCharacteristics.pdf Ramakrishnan, Mathangi and Alias, Nurul Ezaila and Hamzah, Afiq and Tan, Michael Loong Peng and Yusof, Yusmeeraz and Natarajamoorthy, Mathan (2023) Design and analysis of electrical characteristics of 14nm SOI-based trigate gaussian channel junctionless FinFET. In: 1st International Conference on Electronic and Computer Engineering, ECE 2023, 4 July 2023 - 5 July 2023, Virtual, UTM Johor Bahru, Johor, Malaysia. http://dx.doi.org/10.1088/1742-6596/2622/1/012020 |
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TK Electrical engineering. Electronics Nuclear engineering Ramakrishnan, Mathangi Alias, Nurul Ezaila Hamzah, Afiq Tan, Michael Loong Peng Yusof, Yusmeeraz Natarajamoorthy, Mathan Design and analysis of electrical characteristics of 14nm SOI-based trigate gaussian channel junctionless FinFET |
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Planar MOSFETs are reaching their physical limits. To overcome the limitations and improve channel gate control, FinFET technology, which uses many gate devices, is a superior choice while lowering the size of planar MOSFETs even further. In this paper, 14nm Silicon-On-Insulator-based Trigate Gaussian Channel Junctionless FinFET is presented. The gate length of 14nm is considered along with an Equivalent Oxide Thickness of 1nm, 5nm as fin width, and the work function of the gate metal is 4.75eV. The device architecture has a non-uniform doping profile (Gaussian distribution) across the fin’s thickness. It is devised to address the effects of Random Dopant Fluctuations such as channel mobility degradation in Junctionless FinFET based devices. The impact of fin height (Fh), gate dielectric and spacer dielectric on the Drain Induced Barrier Lowering, Subthreshold Swing, drain current of GC-JLFinFET is analyzed. The results show that the Ion=101.5µA/µm and Ion/Ioff is 3.2x107 are obtained for the proposed device structure compared to the existing structure, which has Ion/Ioff of 1.1x107. Furthermore, the proposed design shows better efficiency in short channel characteristics, namely DIBL=25.3 mV/V, Subthreshold Swing=63.88 mV/dec and Transconductance =3.621x105 S/µm. Thus the Gaussian Channel-based FinFET architecture can provide optimum results for Junctionless-based FinFET devices. |
format |
Conference or Workshop Item |
author |
Ramakrishnan, Mathangi Alias, Nurul Ezaila Hamzah, Afiq Tan, Michael Loong Peng Yusof, Yusmeeraz Natarajamoorthy, Mathan |
author_facet |
Ramakrishnan, Mathangi Alias, Nurul Ezaila Hamzah, Afiq Tan, Michael Loong Peng Yusof, Yusmeeraz Natarajamoorthy, Mathan |
author_sort |
Ramakrishnan, Mathangi |
title |
Design and analysis of electrical characteristics of 14nm SOI-based trigate gaussian channel junctionless FinFET |
title_short |
Design and analysis of electrical characteristics of 14nm SOI-based trigate gaussian channel junctionless FinFET |
title_full |
Design and analysis of electrical characteristics of 14nm SOI-based trigate gaussian channel junctionless FinFET |
title_fullStr |
Design and analysis of electrical characteristics of 14nm SOI-based trigate gaussian channel junctionless FinFET |
title_full_unstemmed |
Design and analysis of electrical characteristics of 14nm SOI-based trigate gaussian channel junctionless FinFET |
title_sort |
design and analysis of electrical characteristics of 14nm soi-based trigate gaussian channel junctionless finfet |
publishDate |
2023 |
url |
http://eprints.utm.my/107888/1/NurulEzailaAlias2023_DesignandAnalysisofElectricalCharacteristics.pdf http://eprints.utm.my/107888/ http://dx.doi.org/10.1088/1742-6596/2622/1/012020 |
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