Design and implementation of 32-bit SDRAM memory controller with optimized dynamic power using ASIC

• Main Authors: T., Zheng Hong, Alias, Nurul Ezaila, Tan, Michael Loong Peng, Abdul Wahab, Yasmin
• Format: Conference or Workshop Item
• Published: 2023
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/108377/; http://dx.doi.org/10.1109/RSM59033.2023.10327104
• Institution: Universiti Teknologi Malaysia

Dynamic random access memory (DRAM) is one of the four primary technologies used in the memory hierarchies of a computer system. To improve the operational speed of DRAM, synchronous DRAM (SDRAM) is introduced. Besides, a memory controller is required to manage the data flow between the selected application and the SDRAM. However, a high-speed memory controller that can cope with a high-performance processor will dissipate a lot of dynamic power. Hence, this work proposed a way to reduce the dynamic power dissipation of a 32-bit SDRAM controller through the implementation of clock gating. The design was implemented in Application Specific Integrated Circuit (ASIC) in which the clock gating cells were inserted in DC and further optimized in ICC. As compared to the case without clock gating, a 44.7 % reduction in the dynamic power of the memory controller was observed after implementing clock gating at the end of this work. Next, an average register gating efficiency of 61.6 % was achieved while the voltage drop in the power network is 57.1 mV or 2.54 %. Briefly, the results obtained show that clock gating is an effective way to optimize the dynamic power while maintaining the functionality and performance of the memory controller.