Simultaneous routing and buffer insertion algorithm for minimizing interconnect delay in VLSI layout design

In deep submicron fabrication technology, transistors can now switch much faster, but wire resistances are now larger, and delay due to wires can exceed gate delay. Consequently, the interconnect delay is the dominant factor in the construction of wire routing in very large scale integrated (VLSI) c...

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Bibliographic Details
Main Authors: Husin, Nasir Shaikh, Hani , Mohamed Khalil
Format: Book Section
Language:English
Published: Penerbit UTM 2008
Subjects:
Online Access:http://eprints.utm.my/id/eprint/31034/1/MohamedKhalilHani2008_SimultaneousRoutingandBufferInsertionAlgorithm.pdf
http://eprints.utm.my/id/eprint/31034/
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Institution: Universiti Teknologi Malaysia
Language: English