Simultaneous routing and buffer insertion algorithm for minimizing interconnect delay in VLSI layout design

In deep submicron fabrication technology, transistors can now switch much faster, but wire resistances are now larger, and delay due to wires can exceed gate delay. Consequently, the interconnect delay is the dominant factor in the construction of wire routing in very large scale integrated (VLSI) c...

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Main Authors: Husin, Nasir Shaikh, Hani , Mohamed Khalil
Format: Book Section
Language:English
Published: Penerbit UTM 2008
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Online Access:http://eprints.utm.my/id/eprint/31034/1/MohamedKhalilHani2008_SimultaneousRoutingandBufferInsertionAlgorithm.pdf
http://eprints.utm.my/id/eprint/31034/
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Institution: Universiti Teknologi Malaysia
Language: English
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spelling my.utm.310342017-08-03T00:38:32Z http://eprints.utm.my/id/eprint/31034/ Simultaneous routing and buffer insertion algorithm for minimizing interconnect delay in VLSI layout design Husin, Nasir Shaikh Hani , Mohamed Khalil TK Electrical engineering. Electronics Nuclear engineering In deep submicron fabrication technology, transistors can now switch much faster, but wire resistances are now larger, and delay due to wires can exceed gate delay. Consequently, the interconnect delay is the dominant factor in the construction of wire routing in very large scale integrated (VLSI) circuits, which today, has feature dimensions in the nanometer range. Today, the state-of-the-art circuit design involves as much the engineering of the wires as the design of transistors. Hence, a successful VLSI design today depends heavily on a successful interconnect design. An effective approach for reducing the interconnect delay is buffer insertion (van Ginneken, 1990). In this method, a wire is divided into segments with a buffer inserted between the segments (Cong et al., 1996). Traditionally, buffer insertion is a post-layout optimization technique, implying that the routing paths are first found, and then buffers are inserted in these paths. However, today?s VLSI designs typically apply some form of design reuse utilizing pre-designed cells, or macro blocks. Penerbit UTM 2008 Book Section PeerReviewed application/pdf en http://eprints.utm.my/id/eprint/31034/1/MohamedKhalilHani2008_SimultaneousRoutingandBufferInsertionAlgorithm.pdf Husin, Nasir Shaikh and Hani , Mohamed Khalil (2008) Simultaneous routing and buffer insertion algorithm for minimizing interconnect delay in VLSI layout design. In: Advances In Microelectronics. Penerbit UTM, Skudai, Johor Bahru, pp. 58-82. ISBN 978-983-52-0654-2
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
language English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Husin, Nasir Shaikh
Hani , Mohamed Khalil
Simultaneous routing and buffer insertion algorithm for minimizing interconnect delay in VLSI layout design
description In deep submicron fabrication technology, transistors can now switch much faster, but wire resistances are now larger, and delay due to wires can exceed gate delay. Consequently, the interconnect delay is the dominant factor in the construction of wire routing in very large scale integrated (VLSI) circuits, which today, has feature dimensions in the nanometer range. Today, the state-of-the-art circuit design involves as much the engineering of the wires as the design of transistors. Hence, a successful VLSI design today depends heavily on a successful interconnect design. An effective approach for reducing the interconnect delay is buffer insertion (van Ginneken, 1990). In this method, a wire is divided into segments with a buffer inserted between the segments (Cong et al., 1996). Traditionally, buffer insertion is a post-layout optimization technique, implying that the routing paths are first found, and then buffers are inserted in these paths. However, today?s VLSI designs typically apply some form of design reuse utilizing pre-designed cells, or macro blocks.
format Book Section
author Husin, Nasir Shaikh
Hani , Mohamed Khalil
author_facet Husin, Nasir Shaikh
Hani , Mohamed Khalil
author_sort Husin, Nasir Shaikh
title Simultaneous routing and buffer insertion algorithm for minimizing interconnect delay in VLSI layout design
title_short Simultaneous routing and buffer insertion algorithm for minimizing interconnect delay in VLSI layout design
title_full Simultaneous routing and buffer insertion algorithm for minimizing interconnect delay in VLSI layout design
title_fullStr Simultaneous routing and buffer insertion algorithm for minimizing interconnect delay in VLSI layout design
title_full_unstemmed Simultaneous routing and buffer insertion algorithm for minimizing interconnect delay in VLSI layout design
title_sort simultaneous routing and buffer insertion algorithm for minimizing interconnect delay in vlsi layout design
publisher Penerbit UTM
publishDate 2008
url http://eprints.utm.my/id/eprint/31034/1/MohamedKhalilHani2008_SimultaneousRoutingandBufferInsertionAlgorithm.pdf
http://eprints.utm.my/id/eprint/31034/
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