Iterative RLC models for interconnect delay optimization in VLSI routing algorithms

• Main Authors: Md. Yusof , Zulkifli, Hani, Mohamed Khalil, Shaikh Husin, Nasir, Marsono, Muhammad Nadzir
• Format: Book Section
• Language: English
• Published: Penerbit UTM 2008
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/31035/1/MohamedKhalilHani2008_IterativeRLCModelsforInterconnectDelay.pdf; http://eprints.utm.my/id/eprint/31035/
• Institution: Universiti Teknologi Malaysia

Buffer insertion (van Ginneken, 1990), and wire-sizing techniques (Lillis, Cheng and Lin, 1996) have been widely used to minimize global interconnect delay path between interconnect source and sink points. These techniques rely on delay models (Pileggi, 1995) to estimate buffer insertion points – fr...