Iterative RLC models for interconnect delay optimization in VLSI routing algorithms

Buffer insertion (van Ginneken, 1990), and wire-sizing techniques (Lillis, Cheng and Lin, 1996) have been widely used to minimize global interconnect delay path between interconnect source and sink points. These techniques rely on delay models (Pileggi, 1995) to estimate buffer insertion points – fr...

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Main Authors:	Md. Yusof , Zulkifli, Hani, Mohamed Khalil, Shaikh Husin, Nasir, Marsono, Muhammad Nadzir
Format:	Book Section
Language:	English
Published:	Penerbit UTM 2008
Subjects:	TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/31035/1/MohamedKhalilHani2008_IterativeRLCModelsforInterconnectDelay.pdf http://eprints.utm.my/id/eprint/31035/
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Institution:	Universiti Teknologi Malaysia
Language:	English

id	my.utm.31035
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spelling	my.utm.310352017-08-03T00:42:45Z http://eprints.utm.my/id/eprint/31035/ Iterative RLC models for interconnect delay optimization in VLSI routing algorithms Md. Yusof , Zulkifli Hani, Mohamed Khalil Shaikh Husin, Nasir Marsono, Muhammad Nadzir TK Electrical engineering. Electronics Nuclear engineering Buffer insertion (van Ginneken, 1990), and wire-sizing techniques (Lillis, Cheng and Lin, 1996) have been widely used to minimize global interconnect delay path between interconnect source and sink points. These techniques rely on delay models (Pileggi, 1995) to estimate buffer insertion points – from simple first order linear model (Elmore, 1948) to more complex moment matching techniques (Ismail, Friedman and Neves, 1999a). Thus, interconnect analysis and modeling is of paramount importance in realizing a successful global interconnect routing. For effective buffer insertion point estimation, both source-to-sink and sink-tosource delay estimation may be used (Shaikh-Husin and Khalil- Hani, 2007). As VLSI fabrication technology scales to smaller feature sizes and larger layout areas, global interconnect delay increasingly dominates device delay (Bakoglu, 1990). Penerbit UTM 2008 Book Section PeerReviewed application/pdf en http://eprints.utm.my/id/eprint/31035/1/MohamedKhalilHani2008_IterativeRLCModelsforInterconnectDelay.pdf Md. Yusof , Zulkifli and Hani, Mohamed Khalil and Shaikh Husin, Nasir and Marsono, Muhammad Nadzir (2008) Iterative RLC models for interconnect delay optimization in VLSI routing algorithms. In: Advances In Microelectronics. Penerbit UTM, Skudai, Johor Bahru, pp. 83-93. ISBN 978-983-52-0654-2
institution	Universiti Teknologi Malaysia
building	UTM Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Teknologi Malaysia
content_source	UTM Institutional Repository
url_provider	http://eprints.utm.my/
language	English
topic	TK Electrical engineering. Electronics Nuclear engineering
spellingShingle	TK Electrical engineering. Electronics Nuclear engineering Md. Yusof , Zulkifli Hani, Mohamed Khalil Shaikh Husin, Nasir Marsono, Muhammad Nadzir Iterative RLC models for interconnect delay optimization in VLSI routing algorithms
description	Buffer insertion (van Ginneken, 1990), and wire-sizing techniques (Lillis, Cheng and Lin, 1996) have been widely used to minimize global interconnect delay path between interconnect source and sink points. These techniques rely on delay models (Pileggi, 1995) to estimate buffer insertion points – from simple first order linear model (Elmore, 1948) to more complex moment matching techniques (Ismail, Friedman and Neves, 1999a). Thus, interconnect analysis and modeling is of paramount importance in realizing a successful global interconnect routing. For effective buffer insertion point estimation, both source-to-sink and sink-tosource delay estimation may be used (Shaikh-Husin and Khalil- Hani, 2007). As VLSI fabrication technology scales to smaller feature sizes and larger layout areas, global interconnect delay increasingly dominates device delay (Bakoglu, 1990).
format	Book Section
author	Md. Yusof , Zulkifli Hani, Mohamed Khalil Shaikh Husin, Nasir Marsono, Muhammad Nadzir
author_facet	Md. Yusof , Zulkifli Hani, Mohamed Khalil Shaikh Husin, Nasir Marsono, Muhammad Nadzir
author_sort	Md. Yusof , Zulkifli
title	Iterative RLC models for interconnect delay optimization in VLSI routing algorithms
title_short	Iterative RLC models for interconnect delay optimization in VLSI routing algorithms
title_full	Iterative RLC models for interconnect delay optimization in VLSI routing algorithms
title_fullStr	Iterative RLC models for interconnect delay optimization in VLSI routing algorithms
title_full_unstemmed	Iterative RLC models for interconnect delay optimization in VLSI routing algorithms
title_sort	iterative rlc models for interconnect delay optimization in vlsi routing algorithms
publisher	Penerbit UTM
publishDate	2008
url	http://eprints.utm.my/id/eprint/31035/1/MohamedKhalilHani2008_IterativeRLCModelsforInterconnectDelay.pdf http://eprints.utm.my/id/eprint/31035/
_version_	1643648651987255296

Iterative RLC models for interconnect delay optimization in VLSI routing algorithms

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