System verilog RTL modeling with embedded assertions

• Main Author: Chow, Chee Siang
• Format: Thesis
• Language: English
• Published: 2012
• Subjects: T Technology (General)
• Online Access: http://eprints.utm.my/id/eprint/32554/1/ChowCheeSiangMFKE2012.pdf; http://eprints.utm.my/id/eprint/32554/; http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:77432?queryType=vitalDismax&query=System+verilog+RTL+modeling+with+embedded+assertions&public=true
• Institution: Universiti Teknologi Malaysia

This project has a final goal of developing a new methodology of pre-silicon and post-silicon validation which helps in better IP delivery to SOC system. Hardware Description Language, System Verilog is adopted in doing RTL modeling and System Verilog Assertions are used in verifications. Both design and validation components are combined into single module with pre-defined compiler directive. The conversion of non-synthesizable System Verilog assertions into synthesizable format enables designers to integrate some built in checkers into own design for pre-silicon and post silicon validation. By having synthesizable assertions in the design, the validation cycle can be shorten because some of the testing can be carried out using FPGA. The testing on FPGA can run much faster than simulation which has dependency on simulator tool. Every System Verilog assertion is being modeled as a real hardware component and embedded into design block. The project provides the methodology and examples of how to synthesize System Verilog Assertions using component cascading method to represent temporal expressions used in non-synthesizable assertions.