System verilog RTL modeling with embedded assertions

• Main Author: Chow, Chee Siang
• Format: Thesis
• Language: English
• Published: 2012
• Subjects: T Technology (General)
• Online Access: http://eprints.utm.my/id/eprint/32554/1/ChowCheeSiangMFKE2012.pdf; http://eprints.utm.my/id/eprint/32554/; http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:77432?queryType=vitalDismax&query=System+verilog+RTL+modeling+with+embedded+assertions&public=true
• Institution: Universiti Teknologi Malaysia

This project has a final goal of developing a new methodology of pre-silicon and post-silicon validation which helps in better IP delivery to SOC system. Hardware Description Language, System Verilog is adopted in doing RTL modeling and System Verilog Assertions are used in verifications. Both desig...