Hardware reduction in optical parallel interference cancellation
The success of parallel interference cancellation (PIC) to reduce the multiple access interference in the wireless CDMA communication systems has motivated the communication community to investigate the potential of PIC in the optical CDMA domain. However, the usage of PIC in optical domain will inc...
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| Main Authors: | , , , , |
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| Format: | Conference or Workshop Item |
| Published: |
2007
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| Subjects: | |
| Online Access: | http://eprints.utp.edu.my/429/1/paper.pdf http://www.scopus.com/inward/record.url?eid=2-s2.0-50449085297&partnerID=40&md5=1b55333908ec9a0e4928e2e5cbe38b96 http://eprints.utp.edu.my/429/ |
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| Institution: | Universiti Teknologi Petronas |
| Summary: | The success of parallel interference cancellation (PIC) to reduce the multiple access interference in the wireless CDMA communication systems has motivated the communication community to investigate the potential of PIC in the optical CDMA domain. However, the usage of PIC in optical domain will increase the demand for hardware complexity which results in higher processing time and cost. The hardware complexity increases in the receiver side of Optical PIC (OPIC) when the number of transmitter (users) increases. To overcome these difficulties, we propose a simple and efficient technique based mainly on the OPIC and referred as One Stage OPIC (OS-OPIC). Optical Orthogonal Code (OOC) is adopted as a signature sequence for the performance analysis and a new expression for the error probability is derived. The results show that the proposed method is effective to reduce the hardware complexity, processing time and cost while maintaining the same bit error probability at the cost of increasing the threshold value. ©2007 IEEE.
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