High-Level Synthesis
307 p.
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2017
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Online Access: | http://repository.vnu.edu.vn/handle/VNU_123/30975 |
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oai:112.137.131.14:VNU_123-309752020-05-13T01:41:24Z High-Level Synthesis Coussy, Philippe Morawiec, Adam Engineering 307 p. The successful usage of Hardware Description Languages like VHDL and Verilog in design flows is mainly due to the availability of efficient synthesis methods and tools that enable the translation of RTL designs into optimized gate-level implementations. Many expect that the same approach could be effectively adapted at higher levels of abstraction. In the SoCs context, the traditional IC design methodology relying on EDA tools used in a two stages design flow - a VHDL/Verilog RTL specification, followed by logical and physical synthesis - is indeed no more suitable. Thus, actual complex SoCs need new ESL level tools in order to raise the specification abstraction level up to the algorithmic / behavioral one. However, in order to provide the designers with an efficient automated path to implementation, new high-level synthesis tools and approaches are required. 2017-04-19T02:54:05Z 2017-04-19T02:54:05Z 2008 Book 9781402085888 http://repository.vnu.edu.vn/handle/VNU_123/30975 en 297 p. application/pdf Springer |
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Vietnam National University, Hanoi |
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VNU Library & Information Center |
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Vietnam |
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VNU Digital Repository |
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English |
topic |
Engineering |
spellingShingle |
Engineering High-Level Synthesis |
description |
307 p. |
author2 |
Coussy, Philippe |
author_facet |
Coussy, Philippe |
format |
Book |
title |
High-Level Synthesis |
title_short |
High-Level Synthesis |
title_full |
High-Level Synthesis |
title_fullStr |
High-Level Synthesis |
title_full_unstemmed |
High-Level Synthesis |
title_sort |
high-level synthesis |
publisher |
Springer |
publishDate |
2017 |
url |
http://repository.vnu.edu.vn/handle/VNU_123/30975 |
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1680964592820289536 |