System-level FPGA device driver with high-level synthesis support
We can exploit the standardization of communication abstractions provided by modern high-level synthesis tools like Vivado HLS, Bluespec and SCORE to provide stable system interfaces between the host and PCIe-based FPGA accelerator platforms. At a high level, our FPGA driver attempts to provide CUDA...
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Main Authors: | , , , , |
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Other Authors: | |
Format: | Conference or Workshop Item |
Language: | English |
Published: |
2015
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Subjects: | |
Online Access: | https://hdl.handle.net/10356/81247 http://hdl.handle.net/10220/39202 |
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Institution: | Nanyang Technological University |
Language: | English |