Experimental modules on integrated circuit design using tanner for 0.25 um, 0.35 um, and 0.5 CMOS process

Experimental modules on integrated circuit design using tanner for 0.25 um, 0.35 um, and 0.5 CMOS process

The purpose of this study was to make an Experimental Modules on Integrated Circuit Design Using Tanner for 0.35 um, and 0.5 um CMOS Process. The study includes the development of the environment library for the 0.25 um, 0.35 um, and 0.5 um CMOS processes and the construction, layout designing, DRC,...

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Bibliographic Details
Main Authors: Escano, Ron Alvin V., Katigbak, Bour'bon S., Kumar, Nivas P., Santiago, Jan Romark G.
Format: text
Language:English
Published: Animo Repository 2010
Subjects:
Integrated circuits > Design and construction
Digital integrated circuits > Design and construction
Psychology
Online Access:https://animorepository.dlsu.edu.ph/etd_bachelors/10455
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Institution: De La Salle University
Language: English
Description
Summary:The purpose of this study was to make an Experimental Modules on Integrated Circuit Design Using Tanner for 0.35 um, and 0.5 um CMOS Process. The study includes the development of the environment library for the 0.25 um, 0.35 um, and 0.5 um CMOS processes and the construction, layout designing, DRC, LVS, Parasitic Extraction, and simulation of the circuits. The study also focuses the development of tutorial manuals for using the different designing tools of Tanner EDA, namely, L-Edit and S-Edit, in 0.25 um, 0.35 um CMOS Processes designing environment.

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