Design of CMOS based incremental sigma-delta analog-to-digital converter

• Main Authors: Gorospe, Rey Andrew P., Javier, Jerome Jimm R., Nicolas, April Caezelle M.
• Format: text
• Language: English
• Published: Animo Repository 2010
• Subjects: Analog-to-digital converters; Communication; Electrical and Electronics; Engineering
• Online Access: https://animorepository.dlsu.edu.ph/etd_bachelors/10687
• Institution: De La Salle University

This paper reviews the theoretical operation and describes the design of a 3.3V CMOS Based Incremental Sigma-Delta Analog-to-Digital Converter using 35um CMOS technology. Incremental sigma-delta analog-to-digital converter is a combination of the Nyquist-Rate Dual Slope Converter and Sigma-Delta Converter that converts analog DC inputs into its corresponding digital output. This analog-to-digital converter contains a voltage reference, switched-capacitor integrator, comparator, 1-bit digital-to-analog converter, and an 8-bit digital counter. The objective of this thesis is to design an analog-to-digital converter with an INL of less than 10 LSB, and a DNL of less than 5 LSB. This design is limited to converting only positive DC voltage values, and the initial value for the conversion rate is 4ksps. Simulations were done using T-spice and the layout was designed using L-edit.