Reconfigurable ALU for 16-bit DLX based RISC microprocessor core
Reconfigurable computing is a computing paradigm that combines the flexibility of software with the speed of hardware. It involves changing the hardware configurations of reconfigurable devices such a Field Programmable Logic Arrays (FPGA), in which the functionality of the logic gates in the progra...
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| Main Authors: | , , , , |
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| Format: | text |
| Language: | English |
| Published: |
Animo Repository
2008
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| Subjects: | |
| Online Access: | https://animorepository.dlsu.edu.ph/etd_bachelors/14633 |
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| Institution: | De La Salle University |
| Language: | English |
| Summary: | Reconfigurable computing is a computing paradigm that combines the flexibility of software with the speed of hardware. It involves changing the hardware configurations of reconfigurable devices such a Field Programmable Logic Arrays (FPGA), in which the functionality of the logic gates in the programmable devices can be customized.
Dynamic Partial Reconfiguration (DPR) is a type reconfigurability which changes the configuration of a certain portion inside the FPGA at run-time allows for more flexibility, as hardware could be configured and optimized depending on the functionality required.
This research aims to incorporate DPR on a 16-bit DLX-based RISC Microprocessor Core by designing a Reconfigurable Arithmatic Logic Unit (R-ALU) that changes configuration depending on that computational needs of the microprocessor core. |
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