Reconfigurable ALU for 16-bit DLX based RISC microprocessor core

• Main Authors: Cardenas, Pernell, Lazar, Cristjan, Punzalan, Don Reyan, San Gaspar, Gian Carlo, Santos, Ryan
• Format: text
• Language: English
• Published: Animo Repository 2008
• Subjects: Adaptive computing systems; Field programmable gate arrays
• Online Access: https://animorepository.dlsu.edu.ph/etd_bachelors/14633
• Institution: De La Salle University

Reconfigurable computing is a computing paradigm that combines the flexibility of software with the speed of hardware. It involves changing the hardware configurations of reconfigurable devices such a Field Programmable Logic Arrays (FPGA), in which the functionality of the logic gates in the programmable devices can be customized. Dynamic Partial Reconfiguration (DPR) is a type reconfigurability which changes the configuration of a certain portion inside the FPGA at run-time allows for more flexibility, as hardware could be configured and optimized depending on the functionality required. This research aims to incorporate DPR on a 16-bit DLX-based RISC Microprocessor Core by designing a Reconfigurable Arithmatic Logic Unit (R-ALU) that changes configuration depending on that computational needs of the microprocessor core.