A Full-custom based design of an 8-bit DLX computer architecture
Microprocessor or Central Processing Unit (CPU) serves as the brain and heart of the computer. It is based on different kinds of architecture, one of which is the DLX Computer Architecture. DLX, which is designed by John L. Hennessy and David A. Patterson, embodies the principles of Reduced Instruct...
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| 格式: | text |
| 語言: | English |
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Animo Repository
2010
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| 在線閱讀: | https://animorepository.dlsu.edu.ph/etd_bachelors/14680 |
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| 總結: | Microprocessor or Central Processing Unit (CPU) serves as the brain and heart of the computer. It is based on different kinds of architecture, one of which is the DLX Computer Architecture. DLX, which is designed by John L. Hennessy and David A. Patterson, embodies the principles of Reduced Instruction Set Computer (RISC). It is simple load/store architecture and has efficient pipelining design. Making use of this architecture and the 0.35-micron technology, this thesis aimed to design (full-custom) and implement the data path of CMOS based 8-bit microcontroller core architecture. CMOS conserves power by allowing the processor to be in the sleep state since it does not consume power when it is in idle state. The molecules of the architecture include Instruction Memory, Register Banks, Arithmetic Logic Unit, and Data Memory.
From the research and design of schematic diagrams for each individual module, the netlists were encoded and simulated through T-Spice. The layout was then constructed and extracted through Layout-editor (L-edit) and the extracted spice netlists with parasitic capacitances were again simulated to verify the performance of the microprocessor. The designed modules were then characterized in terms of functionality, speed and general power consumption. |
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