Link layer and transport layer implementation for a serial ATA drive interface to Xilinx ML410 FPGA development board based on a single physically ready input from the physical layer

In an attempt to bridge the knowledge gap between the industry and academic community in the field of secondary storage, an implementation of a Serial ATA Host Controller is done on Virtex-4 ML410 after the controller is interfaced to the MicroBlaze softcore processor. The transport and the link lay...

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Main Authors: Chua, Keith Benedict T., Kong, Seann Kenny S., Kua Chun Ming, Kelvin T.
Format: text
Language:English
Published: Animo Repository 2012
Online Access:https://animorepository.dlsu.edu.ph/etd_bachelors/14799
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Institution: De La Salle University
Language: English
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spelling oai:animorepository.dlsu.edu.ph:etd_bachelors-154412021-11-25T01:36:52Z Link layer and transport layer implementation for a serial ATA drive interface to Xilinx ML410 FPGA development board based on a single physically ready input from the physical layer Chua, Keith Benedict T. Kong, Seann Kenny S. Kua Chun Ming, Kelvin T. In an attempt to bridge the knowledge gap between the industry and academic community in the field of secondary storage, an implementation of a Serial ATA Host Controller is done on Virtex-4 ML410 after the controller is interfaced to the MicroBlaze softcore processor. The transport and the link layer modules are synthesized and simulated using Verilog in Xilinx Integrated Software Environment (ISE) 13.1. It is then interfaced to the MicroBlaze softcore processor with a system clock of 50 MHz Xilinx Platform Studio (XPS) 12.4. In order to verify results, a module stimulating the hard disk is used. The MicroBlaze acts as the top level controller by providing control inputs to the SATA core and displaying the outputs via the HyperTerminal. 2012-01-01T08:00:00Z text https://animorepository.dlsu.edu.ph/etd_bachelors/14799 Bachelor's Theses English Animo Repository
institution De La Salle University
building De La Salle University Library
continent Asia
country Philippines
Philippines
content_provider De La Salle University Library
collection DLSU Institutional Repository
language English
description In an attempt to bridge the knowledge gap between the industry and academic community in the field of secondary storage, an implementation of a Serial ATA Host Controller is done on Virtex-4 ML410 after the controller is interfaced to the MicroBlaze softcore processor. The transport and the link layer modules are synthesized and simulated using Verilog in Xilinx Integrated Software Environment (ISE) 13.1. It is then interfaced to the MicroBlaze softcore processor with a system clock of 50 MHz Xilinx Platform Studio (XPS) 12.4. In order to verify results, a module stimulating the hard disk is used. The MicroBlaze acts as the top level controller by providing control inputs to the SATA core and displaying the outputs via the HyperTerminal.
format text
author Chua, Keith Benedict T.
Kong, Seann Kenny S.
Kua Chun Ming, Kelvin T.
spellingShingle Chua, Keith Benedict T.
Kong, Seann Kenny S.
Kua Chun Ming, Kelvin T.
Link layer and transport layer implementation for a serial ATA drive interface to Xilinx ML410 FPGA development board based on a single physically ready input from the physical layer
author_facet Chua, Keith Benedict T.
Kong, Seann Kenny S.
Kua Chun Ming, Kelvin T.
author_sort Chua, Keith Benedict T.
title Link layer and transport layer implementation for a serial ATA drive interface to Xilinx ML410 FPGA development board based on a single physically ready input from the physical layer
title_short Link layer and transport layer implementation for a serial ATA drive interface to Xilinx ML410 FPGA development board based on a single physically ready input from the physical layer
title_full Link layer and transport layer implementation for a serial ATA drive interface to Xilinx ML410 FPGA development board based on a single physically ready input from the physical layer
title_fullStr Link layer and transport layer implementation for a serial ATA drive interface to Xilinx ML410 FPGA development board based on a single physically ready input from the physical layer
title_full_unstemmed Link layer and transport layer implementation for a serial ATA drive interface to Xilinx ML410 FPGA development board based on a single physically ready input from the physical layer
title_sort link layer and transport layer implementation for a serial ata drive interface to xilinx ml410 fpga development board based on a single physically ready input from the physical layer
publisher Animo Repository
publishDate 2012
url https://animorepository.dlsu.edu.ph/etd_bachelors/14799
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