A 0.35um low voltage ADC using Delta-Sigma modulator with CIC decimation filter
This study focused on the design and characterization of a 10-bit Delta-Sigma Analogto- Digital Converter (DS-ADC) that can operate at 1.5V supply using 0.35um technology that is normally intended to work at 3.3V. The design has an oversampling ratio (OSR) of 128, a signal bandwidth of 4 KHz, which...
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oai:animorepository.dlsu.edu.ph:etd_masteral-108442022-05-10T01:20:56Z A 0.35um low voltage ADC using Delta-Sigma modulator with CIC decimation filter Abad, Alexander C. This study focused on the design and characterization of a 10-bit Delta-Sigma Analogto- Digital Converter (DS-ADC) that can operate at 1.5V supply using 0.35um technology that is normally intended to work at 3.3V. The design has an oversampling ratio (OSR) of 128, a signal bandwidth of 4 KHz, which covers the human voice bandwidth, and a maximum sampling frequency of 1.024 MHz. The design is composed of a 1st Order Delta-Sigma Modulator and a 2nd Order Cascaded Integrator Comb (CIC) decimation filter as its digital signal processor (DSP). The DS-ADC was designed, characterized and implemented using Tanner tools and LTSpice tool. 2011-02-01T08:00:00Z text application/pdf https://animorepository.dlsu.edu.ph/etd_masteral/4006 https://animorepository.dlsu.edu.ph/context/etd_masteral/article/10844/viewcontent/CDTG004883_P.pdf Master's Theses English Animo Repository Analog-to-digital converters Electrical and Electronics |
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Analog-to-digital converters Electrical and Electronics Abad, Alexander C. A 0.35um low voltage ADC using Delta-Sigma modulator with CIC decimation filter |
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This study focused on the design and characterization of a 10-bit Delta-Sigma Analogto- Digital Converter (DS-ADC) that can operate at 1.5V supply using 0.35um technology that is normally intended to work at 3.3V. The design has an oversampling ratio (OSR) of 128, a signal bandwidth of 4 KHz, which covers the human voice bandwidth, and a maximum sampling frequency of 1.024 MHz. The design is composed of a 1st Order Delta-Sigma Modulator and a 2nd Order Cascaded Integrator Comb (CIC) decimation filter as its digital signal processor (DSP). The DS-ADC was designed, characterized and implemented using Tanner tools and LTSpice tool. |
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text |
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Abad, Alexander C. |
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Abad, Alexander C. |
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Abad, Alexander C. |
title |
A 0.35um low voltage ADC using Delta-Sigma modulator with CIC decimation filter |
title_short |
A 0.35um low voltage ADC using Delta-Sigma modulator with CIC decimation filter |
title_full |
A 0.35um low voltage ADC using Delta-Sigma modulator with CIC decimation filter |
title_fullStr |
A 0.35um low voltage ADC using Delta-Sigma modulator with CIC decimation filter |
title_full_unstemmed |
A 0.35um low voltage ADC using Delta-Sigma modulator with CIC decimation filter |
title_sort |
0.35um low voltage adc using delta-sigma modulator with cic decimation filter |
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Animo Repository |
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2011 |
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https://animorepository.dlsu.edu.ph/etd_masteral/4006 https://animorepository.dlsu.edu.ph/context/etd_masteral/article/10844/viewcontent/CDTG004883_P.pdf |
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