Branch optimization to improve branch prediction for P6 superpipeline microarchitecture

In superpipeline microarchitecture, the instruction execution cycle is divided into many stages. This type of microarchitecture increases the throughput or the number of instructions executed in a certain time period. But, pipeline stalls due to branch misprediction causes severe degradation in the...

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主要作者: Uy, Roger Luis
格式: text
語言:English
出版: Animo Repository 1999
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在線閱讀:https://animorepository.dlsu.edu.ph/etd_masteral/2291
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