The qualification of a C4 bump rework

• Main Authors: Crafts, Doug, Jeng, Kevin, Bruton, Gillian, McGovern, Eamonn, Tirol, D.J. Rean D., Esteban, Carlo
• Format: text
• Published: Animo Repository 1999
• Subjects: Tinplate—Testing; Reliability (Engineering); Engineering Physics; Physical Sciences and Mathematics; Physics
• Online Access: https://animorepository.dlsu.edu.ph/faculty_research/13347
• Institution: De La Salle University

In response to an excursion at the Ireland Fab Operations, involving the use of a high Sn bump plating bath efforts were under taken to develop a rework process to save ~ S200M worth of inventory. Sn concentration was found to be 1% higher vs the typical due to the absence of 2-naphtol a Sn inhibitor present in plating solutions in equilibrium. Wafers processed exhibited very poor bump reflow quality and had gross electrical opens and high resistance failures. Failure analysis revealed severe non-wetting, base layer delamination and base layer intermetallic abnormalities. Further analysis showed higher a thicker Sn-Ni intermetallic layer also resulting in a thicker layer of the porous vanadium oxide. An etch process was developed involving higher concentrations of Methyl Sulphonic, Sulfuric, Nitric and Flouric acids. C4 Bumps and the intermetallics were stripped. Wafers were then reprocessed to get a second round of NiV and Sn/Pb bumps. Finished wafers were assembled subjected to temperature cycling (500x -55 to 125°C), biased HAST (100h, 85% RH, 135°C, 3.3V) and extend bake (168h, 200°C). Products successfully passed reliability requirements