Integrating FPGA design flow in teaching computer architecture in the undergraduate computing engineering curriculum using a scalable computer architecture

• Main Author: Llorente, Cesar A.
• Format: text
• Published: Animo Repository 2009
• Subjects: Computer architecture; Field programmable gate arrays; Computer and Systems Architecture
• Online Access: https://animorepository.dlsu.edu.ph/faculty_research/8117
• Institution: De La Salle University

Teaching computer architecture concepts in the undergraduate computer engineering curriculum in Philippine colleges and universities offering computer engineering programs poses some challenges and difficulties. Typical approaches are to discuss the underlying concepts based on the Complex Instruction Set Computer (CISC) and the Reduced Instruction Set Computer (RISC) architectures. However, reinforcing concepts through hands on activities that exposes students to the actual design and implementation of a computer architecture are still lacking in the computer engineering curricula in the Philippines. The inclusion in the undergraduate computer engineering courses of Hardware Description language (HDL) and the introduction of Field Programmable Gate Arrays (FPGA) Development Platforms, provided students the possibility of actually designing and implementing complex digital systems. The Scalable Computer Architecture (SCA) described in this work, is a computer archiiecture that can be used as a platform lo provide students opportunity to design and implement a CISC Architecture. A series of laboratory experiments enable the students to synthesize and simulate the SCA using Electronic Design Automation (EDA) tools such as Quartus II from Altera Corporation or ISE from Xilinx Corporation. Actual implementation of the SCA can then be carried out by downloading the design on FPGA Development Platforms. The functionality of the SCA is enhanced through machine problems that must be carried out by the students in each laboratory experiments. For example, instructions are added to the initial instruction set of the SCA. The inclusion of instructions necessitate also designing and implementing the corresponding subsystem using HDL. Thus, the capability of the SCA is scaled up in each succeeding laboratory activity. By starting with a base functionality of the SCA and subsequently adding functionality, learning of computer architecture concepts are reinforced. Providing students the opportunity to design and implement additional functionality of the SCA with scaled complexity through machine problems in each experiment, enable them to develop creative thinking and design skills while honing their skills with the use of industry-standard design tools.