Bit serial modular multiplication on FPGA

• Main Authors: Nazar, Medi A., Kittitornkun, Surin
• Format: text
• Published: Animo Repository 2005
• Subjects: Systolic array circuits; Field programmable gate arrays; Public key cryptography; Electrical and Computer Engineering
• Online Access: https://animorepository.dlsu.edu.ph/faculty_research/8206
• Institution: De La Salle University

RSA algorithm is a cryptographic algorithm that requires repeated modular multiplications of very large operands. In RSA, the higher the security the larger is the operand size, which may reduce the clock rate and result to lower throughput. This paper presents a fully systolic linear-array for the computation of Montgomery modular multiplication that is implemented using FPGA. Our fully systolic design shows that a high and nearly constant clock rate is achievable regardless of the size of the operand. As compared with the non-fully systolic architecture, our design offers higher frequency that yields a higher throughput rate and a lower area-time product. As compared to another existing systolic architecture, our design achieved faster execution time. The total execution time of our multiplier when n= 1024 is 17 · 95 µs for one modular multiplication, where n 1s the length of the modulus.