A Novel Low-Power Synchronous Preamble Data Line Chip Design for Oscillator Control Interface

• المؤلفون الرئيسيون: Chen, Shih-Lun, Chi, Tsun-Kuang, Tuan, Min-Chun, Chen, Chiung-An, Wang, Liang-Hung, Chiang, Wei-Yuan, Lin, Ming-Yi, Abu, Patricia Angela R
• التنسيق: text
• منشور في: Archīum Ateneo 2020
• الموضوعات: SPI; digital signal process; communication protocols; CMOS digital integrated circuit; field-programmable gate array (FPGA); electronic device measurement and very-large-scale integration (VLSI); Computer Sciences; Databases and Information Systems
• الوصول للمادة أونلاين: https://archium.ateneo.edu/discs-faculty-pubs/314; https://archium.ateneo.edu/cgi/viewcontent.cgi?article=1285&context=discs-faculty-pubs

In this paper, a novel low-power synchronous preamble data line protocol chip design for serial communication is proposed. The serial communication only uses two wires, chip select (CS) and secure digital (SD), to transmit and receive data between two devices. The proposed protocol aims to use a few...