A Novel Low-Power Synchronous Preamble Data Line Chip Design for Oscillator Control Interface
In this paper, a novel low-power synchronous preamble data line protocol chip design for serial communication is proposed. The serial communication only uses two wires, chip select (CS) and secure digital (SD), to transmit and receive data between two devices. The proposed protocol aims to use a few...
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Main Authors: | Chen, Shih-Lun, Chi, Tsun-Kuang, Tuan, Min-Chun, Chen, Chiung-An, Wang, Liang-Hung, Chiang, Wei-Yuan, Lin, Ming-Yi, Abu, Patricia Angela R |
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Format: | text |
Published: |
Archīum Ateneo
2020
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Subjects: | |
Online Access: | https://archium.ateneo.edu/discs-faculty-pubs/314 https://archium.ateneo.edu/cgi/viewcontent.cgi?article=1285&context=discs-faculty-pubs |
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Institution: | Ateneo De Manila University |
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