Performance and wirability driven layout for row-based FPGAs

Performance and wirability driven layout for row-based FPGAs

10.1155/1998/57380

Saved in:
Bibliographic Details
Main Authors: Nag, S, Roy, K
Other Authors: LIFE SCIENCES INSTITUTE
Format: Article
Published: Hindawi Limited 2020
Subjects:
Electric network analysis
Electric wiring
Integrated circuit layout
Perturbation techniques
Routers
Post-layout timing analyzers
Row-based field programmable gate arrays (FPGA)
Field programmable gate arrays
Online Access:https://scholarbank.nus.edu.sg/handle/10635/181142
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: National University of Singapore

Internet

https://scholarbank.nus.edu.sg/handle/10635/181142

Similar Items