Performance and wirability driven layout for row-based FPGAs

10.1155/1998/57380

Saved in:

Bibliographic Details
Main Authors:	Nag, S, Roy, K
Other Authors:	LIFE SCIENCES INSTITUTE
Format:	Article
Published:	Hindawi Limited 2020
Subjects:	Electric network analysis Electric wiring Integrated circuit layout Perturbation techniques Routers Post-layout timing analyzers Row-based field programmable gate arrays (FPGA) Field programmable gate arrays
Online Access:	https://scholarbank.nus.edu.sg/handle/10635/181142
Tags:	Add Tag No Tags, Be the first to tag this record!
Institution:	National University of Singapore

id	sg-nus-scholar.10635-181142
record_format	dspace
spelling	sg-nus-scholar.10635-1811422023-11-01T08:15:29Z Performance and wirability driven layout for row-based FPGAs Nag, S Roy, K LIFE SCIENCES INSTITUTE Electric network analysis Electric wiring Integrated circuit layout Perturbation techniques Routers Post-layout timing analyzers Row-based field programmable gate arrays (FPGA) Field programmable gate arrays 10.1155/1998/57380 VLSI Design 7 4 353-364 2020-10-27T09:58:39Z 2020-10-27T09:58:39Z 1998 Article Nag, S, Roy, K (1998). Performance and wirability driven layout for row-based FPGAs. VLSI Design 7 (4) : 353-364. ScholarBank@NUS Repository. https://doi.org/10.1155/1998/57380 1065514X https://scholarbank.nus.edu.sg/handle/10635/181142 Attribution 4.0 International http://creativecommons.org/licenses/by/4.0/ Hindawi Limited Unpaywall 20201031
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
topic	Electric network analysis Electric wiring Integrated circuit layout Perturbation techniques Routers Post-layout timing analyzers Row-based field programmable gate arrays (FPGA) Field programmable gate arrays
spellingShingle	Electric network analysis Electric wiring Integrated circuit layout Perturbation techniques Routers Post-layout timing analyzers Row-based field programmable gate arrays (FPGA) Field programmable gate arrays Nag, S Roy, K Performance and wirability driven layout for row-based FPGAs
description	10.1155/1998/57380
author2	LIFE SCIENCES INSTITUTE
author_facet	LIFE SCIENCES INSTITUTE Nag, S Roy, K
format	Article
author	Nag, S Roy, K
author_sort	Nag, S
title	Performance and wirability driven layout for row-based FPGAs
title_short	Performance and wirability driven layout for row-based FPGAs
title_full	Performance and wirability driven layout for row-based FPGAs
title_fullStr	Performance and wirability driven layout for row-based FPGAs
title_full_unstemmed	Performance and wirability driven layout for row-based FPGAs
title_sort	performance and wirability driven layout for row-based fpgas
publisher	Hindawi Limited
publishDate	2020
url	https://scholarbank.nus.edu.sg/handle/10635/181142
_version_	1781792439048077312

Performance and wirability driven layout for row-based FPGAs

Similar Items