Performance and wirability driven layout for row-based FPGAs

• Main Authors: Nag, S, Roy, K
• Other Authors: LIFE SCIENCES INSTITUTE
• Format: Article
• Published: Hindawi Limited 2020
• Subjects: Electric network analysis; Electric wiring; Integrated circuit layout; Perturbation techniques; Routers; Post-layout timing analyzers; Row-based field programmable gate arrays (FPGA); Field programmable gate arrays
• Online Access: https://scholarbank.nus.edu.sg/handle/10635/181142
• Institution: National University of Singapore

10.1155/1998/57380