Low-energy and area-efficient tri-level switching scheme for SAR ADC
A novel low-energy tri-level switching scheme for low-power successive approximation register (SAR) ADC is proposed. With the input common-mode voltage (Vcm) designed to be exactly half of the reference voltage (Vref ), the switching energy of the proposed switching scheme is reduced by 96.89% a...
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| Main Authors: | , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
2013
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/100633 http://hdl.handle.net/10220/13270 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | A novel low-energy tri-level switching scheme for low-power successive
approximation register (SAR) ADC is proposed. With the input
common-mode voltage (Vcm) designed to be exactly half of the reference
voltage (Vref ), the switching energy of the proposed switching
scheme is reduced by 96.89% as compared with the conventional architecture.
Besides the large energy saving, the proposed switching
scheme also reduces the number of capacitors in the ADC capacitor
array by 75%, which in turn results in an area-efficient SAR ADC. |
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