Analysis and reduction of mismatch in silicon neurons

• Main Authors: Shuo, Sun, Basu, Arindam
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/100795; http://hdl.handle.net/10220/18170
• Institution: Nanyang Technological University

In this paper, we describe a methodical approach for reducing errors due to mismatch in neuron circuits. We chose the neuron's current-frequency (f-i) curve as the desired output and use a sensitivity analysis to determine which transistors contribute most significantly to its variation. This allows us to identify the most critical transistors that need to be matched. For the special case in which floating-gate (FG) transistors are used to reduce this mismatch, we propose a method to further reduce the number of FG devices to be used in the circuit resulting in a corresponding reduction in “calibration” time. In addition to reducing mismatch between neurons, the usage of FG devices allows the user to independently set the parameters of each neuron. Since the calibration is based on f-i curve, it can be obtained through address-event representation (AER) circuits that are included in the neuron array for normal functionality. We use one example of commonly used integrate and fire neuron to illustrate this mismatch correction procedure. The method presented allows the corrected neurons to compute both rate codes and spike time codes in a mismatch resilient fashion