Reliable 3-D clock-tree synthesis considering nonlinear capacitive TSV model with electrical–thermal–mechanical coupling

• Main Authors: P. D., Sai Manoj, Yu, Hao, Yang Shang, Chuan Seng Tan, Sung Kyu Lim
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Computer science and engineering::Computer applications::Computer-aided engineering
• Online Access: https://hdl.handle.net/10356/100898; http://hdl.handle.net/10220/18217
• Institution: Nanyang Technological University

A robust physical design of 3-D IC requires investigation on through-silicon via (TSV). The large temperatures and stress gradients can severely affect TSV delay with large variation. The traditional physical model treats TSV as a resistor with linear electrical-thermal dependence, which ignores the...