A 60GHz on-chip antenna in standard CMOS silicon technology

• Main Authors: Yang, Wanlan, Ma, Kaixue, Yeo, Kiat Seng, Lim, Wei Meng
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/101570; http://hdl.handle.net/10220/16333
• Institution: Nanyang Technological University

This paper presents a compact and efficient 60-GHz on chip antenna that may be realized with the back-end-of-line process of standard CMOS silicon Technology on low resistivity 10 Ω.cm silicon substrate. A planar tab monopole antenna structure is adopted and the feeding network is designed with 50Ω substrate-shielded CPW line. The designed antenna has a compact size of 1.5mm*1.0mm, including feed line and pads which are the integral parts of the antenna. Ansoft HFSS is used for design simulation with results centered at 60 GHz as following: the maximum gain is around 0.1dBi, the radiation efficiency is around 39%, the VSWR is less than 1.5 from 51.5 GHz to 70.6 GHz and the minimum return loss is around -36dB to achieve a better quality of impedance matching. The designed on-chip antenna can be used for the integration of a 60 GHz single-chip transceiver.