A 60GHz on-chip antenna in standard CMOS silicon technology
This paper presents a compact and efficient 60-GHz on chip antenna that may be realized with the back-end-of-line process of standard CMOS silicon Technology on low resistivity 10 Ω.cm silicon substrate. A planar tab monopole antenna structure is adopted and the feeding network is designed with 50Ω...
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sg-ntu-dr.10356-1015702020-03-07T13:24:50Z A 60GHz on-chip antenna in standard CMOS silicon technology Yang, Wanlan Ma, Kaixue Yeo, Kiat Seng Lim, Wei Meng School of Electrical and Electronic Engineering IEEE Asia Pacific Conference on Circuits and Systems (2012 : Kaohsiung, Taiwan) DRNTU::Engineering::Electrical and electronic engineering This paper presents a compact and efficient 60-GHz on chip antenna that may be realized with the back-end-of-line process of standard CMOS silicon Technology on low resistivity 10 Ω.cm silicon substrate. A planar tab monopole antenna structure is adopted and the feeding network is designed with 50Ω substrate-shielded CPW line. The designed antenna has a compact size of 1.5mm*1.0mm, including feed line and pads which are the integral parts of the antenna. Ansoft HFSS is used for design simulation with results centered at 60 GHz as following: the maximum gain is around 0.1dBi, the radiation efficiency is around 39%, the VSWR is less than 1.5 from 51.5 GHz to 70.6 GHz and the minimum return loss is around -36dB to achieve a better quality of impedance matching. The designed on-chip antenna can be used for the integration of a 60 GHz single-chip transceiver. 2013-10-10T02:29:54Z 2019-12-06T20:40:43Z 2013-10-10T02:29:54Z 2019-12-06T20:40:43Z 2012 2012 Conference Paper Yang, W., Ma, K., Yeo, K. S., & Lim, W. M. (2012). A 60GHz on-chip antenna in standard CMOS silicon technology. 2012 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp.252-255. https://hdl.handle.net/10356/101570 http://hdl.handle.net/10220/16333 10.1109/APCCAS.2012.6419019 en |
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DRNTU::Engineering::Electrical and electronic engineering Yang, Wanlan Ma, Kaixue Yeo, Kiat Seng Lim, Wei Meng A 60GHz on-chip antenna in standard CMOS silicon technology |
| description |
This paper presents a compact and efficient 60-GHz on chip antenna that may be realized with the back-end-of-line process of standard CMOS silicon Technology on low resistivity 10 Ω.cm silicon substrate. A planar tab monopole antenna structure is adopted and the feeding network is designed with 50Ω substrate-shielded CPW line. The designed antenna has a compact size of 1.5mm*1.0mm, including feed line and pads which are the integral parts of the antenna. Ansoft HFSS is used for design simulation with results centered at 60 GHz as following: the maximum gain is around 0.1dBi, the radiation efficiency is around 39%, the VSWR is less than 1.5 from 51.5 GHz to 70.6 GHz and the minimum return loss is around -36dB to achieve a better quality of impedance matching. The designed on-chip antenna can be used for the integration of a 60 GHz single-chip transceiver. |
| author2 |
School of Electrical and Electronic Engineering |
| author_facet |
School of Electrical and Electronic Engineering Yang, Wanlan Ma, Kaixue Yeo, Kiat Seng Lim, Wei Meng |
| format |
Conference or Workshop Item |
| author |
Yang, Wanlan Ma, Kaixue Yeo, Kiat Seng Lim, Wei Meng |
| author_sort |
Yang, Wanlan |
| title |
A 60GHz on-chip antenna in standard CMOS silicon technology |
| title_short |
A 60GHz on-chip antenna in standard CMOS silicon technology |
| title_full |
A 60GHz on-chip antenna in standard CMOS silicon technology |
| title_fullStr |
A 60GHz on-chip antenna in standard CMOS silicon technology |
| title_full_unstemmed |
A 60GHz on-chip antenna in standard CMOS silicon technology |
| title_sort |
60ghz on-chip antenna in standard cmos silicon technology |
| publishDate |
2013 |
| url |
https://hdl.handle.net/10356/101570 http://hdl.handle.net/10220/16333 |
| _version_ |
1681041926631981056 |