Integrated circuits design for neural recording sensor interface

• Main Authors: Xiaodan, Zou, Lei, Liu, Tan, Yung Sern, Je, Minkyu, Yeo, Kiat Seng
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/102077; http://hdl.handle.net/10220/16343
• Institution: Nanyang Technological University

Neural signal recording is attracting more and more attention, as it provides an necessary approach to read brain activities, understand the brain operation and restore the lost motor function of the body. One of the most important modules in the neural recording system is the sensor interface IC, which captures, amplifies, filters, and digitizes the weak neural signal. In order to preserve free movement of the subject under testing and minimize the risk of infection, the sensor interface IC is usually implanted under the skin or skull with wireless transmission. The nature of the neural signal and its recording scenarios impose rigid design specifications to the sensor interface IC, such as low noise, low power, low cut-off frequency and minimum chip size. Many designs have been reported recently to tackle these challenges in neural recording system. In this paper, design techniques for neural recording sensor interface IC will be introduced, including the design of system architecture and neural amplifier. Methods to realize low power, low noise and low cut-off frequency are investigated. In addition, the methods to achieve system power and area optimization are also discussed.