0.6mW 6.3 GHz 40nm CMOS divide-by-2/3 prescaler using heterodyne phase-locking technique

• Main Authors: Yu, Xiao Peng, Lu, Zhenghao, Lim, Wei Meng, Yeo, Kiat Seng
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2013
• 主題: DRNTU::Engineering::Electrical and electronic engineering
• 在線閱讀: https://hdl.handle.net/10356/102377; http://hdl.handle.net/10220/16515
• 機構: Nanyang Technological University

A dual-modulus prescaler based on the heterodyne phase-locking technique is presented. Different to the conventional LC tank based phase-locked loop, by directly locking at two injection-locked ring oscillators simultaneously, a dual-modulus operation is achieved while a wide-range operating, signif...