0.6mW 6.3 GHz 40nm CMOS divide-by-2/3 prescaler using heterodyne phase-locking technique

• Main Authors: Yu, Xiao Peng, Lu, Zhenghao, Lim, Wei Meng, Yeo, Kiat Seng
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/102377; http://hdl.handle.net/10220/16515
• Institution: Nanyang Technological University

A dual-modulus prescaler based on the heterodyne phase-locking technique is presented. Different to the conventional LC tank based phase-locked loop, by directly locking at two injection-locked ring oscillators simultaneously, a dual-modulus operation is achieved while a wide-range operating, significantly reduced settling time and low power consumption are achieved. Implemented in a standard 40nm CMOS process, the proposed divide-by-2 and 3 dual-modulus prescaler achieves an operating frequency of 6.3GHz with a measured power consumption of 0.6mW from a 1.1V supply.