A memory-efficient high-throughput architecture for lifting-based multi-level 2-D DWT

In this paper, we present a novel memory-efficient high-throughput scalable architecture for multi-level 2-D DWT. We studied the existing DWT architectures and observed that data scanning method has a significant impact on the memory efficiency of DWT architecture. We propose a novel parallel stripe...

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Bibliographic Details
Main Authors: Hu, Yusong, Jong, Ching Chuen
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2013
Subjects:
Online Access:https://hdl.handle.net/10356/104036
http://hdl.handle.net/10220/16974
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Institution: Nanyang Technological University
Language: English