A memory-efficient high-throughput architecture for lifting-based multi-level 2-D DWT

• المؤلفون الرئيسيون: Hu, Yusong, Jong, Ching Chuen
• مؤلفون آخرون: School of Electrical and Electronic Engineering
• التنسيق: مقال
• اللغة: English
• منشور في: 2013
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/104036; http://hdl.handle.net/10220/16974
• المؤسسة: Nanyang Technological University

In this paper, we present a novel memory-efficient high-throughput scalable architecture for multi-level 2-D DWT. We studied the existing DWT architectures and observed that data scanning method has a significant impact on the memory efficiency of DWT architecture. We propose a novel parallel stripe...