A high speed low power CAM with a parity bit and power-gated ML sensing

• Main Authors: Do, Anh Tuan, Chen, Shoushun, Kong, Zhi Hui, Yeo, Kiat Seng
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2013
• 主題: DRNTU::Engineering::Electrical and electronic engineering
• 在線閱讀: https://hdl.handle.net/10356/104828; http://hdl.handle.net/10220/16855

Content addressable memory (CAM) offers high-speed search function in a single clock cycle. Due to its parallel match-line (ML) comparison, CAM is power-hungry. Thus, robust, high-speed and low-power ML sense amplifiers are highly sought-after in CAM designs. In this paper, we introduce a parity bit...