New hardware and power efficient sporadic logarithmic shifters for DSP applications

• Main Authors: Chen, Jiajia, Chang, Chip-Hong, Wang, Yujia, Zhao, Juan, Rahardja, Susanto
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2019
• Subjects: Digital IC Design; Digital Signal Processing; DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/105840; http://hdl.handle.net/10220/47854; http://dx.doi.org/10.1109/TCAD.2017.2740300
• Institution: Nanyang Technological University

Shifting an input data by variable amounts is commonly found in arithmetic operations, data encoding and bit-indexing. Although some shift amounts along the entire shift range are not required, the typical realization by a full-range logarithm shifter requires full implementation and therefore suffers from complexity and power overhead. In this paper, the notion of sporadic logarithmic shifter is introduced for the first time, and a new design methodology is proposed for its optimization. By reusing parts of existing substructure of conventional logarithmic shifter or post-multiplexing the hardwired shifts, contagious subranges of desirable shift amounts are successively realized. Synthesis results on 8-bit and 16-bit sporadic logarithmic shifters show average ASIC area and power savings of up to 73.24% and 63.90% respectively, over conventional logarithmic shifters. In addition, by applying the proposed sporadic logarithmic shifters to the DCT architecture, at least 47.5% area savings and 2.9% power savings can be achieved over two constant multipliers based DCT architectures reported in the literature.