Five-stage pipelined RISC-V SoC design

• المؤلف الرئيسي: Yang, Yulong
• مؤلفون آخرون: Gwee Bah Hwee
• التنسيق: Thesis-Master by Coursework
• اللغة: English
• منشور في: Nanyang Technological University 2025
• الموضوعات: Engineering; Digital IC; RISC-V
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/183432

With the rapid development of the Internet of Things (IoT), embedded systems and artificial intelligence, there is an increasing demand for low-power and high-performance processors. RISC-V, as an open-source, streamlined and scalable instruction set architecture, is gradually becoming an ideal choi...