Single-event-transient resilient memory for DSP in space applications

• Main Authors: Lwin, Ne Kyaw Zwa, Sivaramakrishnan, H., Chong, Kwen-Siong, Lin, Tong, Shu, Wei, Chang, Joseph S.
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2019
• Subjects: Engineering::Electrical and electronic engineering; Computer Architecture; SRAM Cells
• Online Access: https://hdl.handle.net/10356/106084; http://hdl.handle.net/10220/49031; https://dx.doi.org/10.1109/ICDSP.2018.8631639
• Institution: Nanyang Technological University

We present a radiation-hardened-by-design (RHBD) memory design that mitigates Single-Event-Transients (SETs), Single-Event-Upsets (SEUs) and Dual-Event-Upsets (DEUs), hence significantly enhancing the reliability of digital signal processors (DSPs) for space applications. We achieve these attributes by combining a Triple-Interlocked Cell (TICE) SRAM cell array and a Triple Modular Redundancy (TMR) voter. The TICE SRAM cells therein self-correct SEUs and DEUs. The TMR voter eliminates SETs. Our proposed RHBD TICE SRAM cells integrated with the TMR voter are also hardened by the layout/sizing RHBD practices. By means of the 128×9-bit memory implementation @ 65nm CMOS, we show that our memory design is inherent SEUand DEU-tolerant, and has 94.83% SET reduction and 92.05% Triple-Event-Upset (TEU) reduction when compared to the memory design embodying the 8-transistor (8-T) SRAM cells.