A 0.9-µ A quiescent current output-capacitorless LDO regulator with adaptive power transistors in 65-nm CMOS

• Main Authors: Chong, Sau Siong, Chan, Pak Kwong
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/106620; http://hdl.handle.net/10220/16650; http://dx.doi.org/10.1109/TCSI.2012.2215392
• Institution: Nanyang Technological University

An ultra-low quiescent current output-capacitorless low-dropout (OCL-LDO) regulator with adaptive power transistors technique is presented in this paper. The proposed technique permits the regulator to transform itself between 2-stage and 3-stage cascaded topologies with respective power transistor, depending on the load current condition. As such, it enables the OCL-LDO regulator to achieve ultra-low power consumption, high stability and good transient response without the need of off-chip capacitor at the output. The proposed LDO regulator has been implemented and fabricated in a UMC 65-nm CMOS process. It occupies an active area of 0.017 mm$^{2}$ . The measured results have shown that the proposed circuit consumes a quiescent current of 0.9 $mu$ A at no load, regulating the output at 1 V from a voltage supply of 1.2 V. It achieves full range stability from 0 to 100 mA load current at a maximum 100 pF parasitic capacitance load. The measured transient output voltage is 68.8 mV when load current is stepped from 0 to 100 mA in 300 ns with ${rm C}_{rm L} = 100$ pF. The recovery time is about 6 $mu$s. Compared to previously reported counterparts, the proposed OCL-LDO regulator shows a significant improvement in term of OCL-LDO transient figure-of-merit (FOM) as well as balanced performance parameters in terms of PSR, line regulation and load regulation.