High linearity 8-bit VCO-based cascaded ΣΔADC for digital DC-DC converters

• Main Authors: Foong, Huey Chian, Tan, Meng Tong, Zheng, Yuanjin
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2013
• 主題: DRNTU::Engineering::Electrical and electronic engineering
• 在線閱讀: https://hdl.handle.net/10356/106782; http://hdl.handle.net/10220/17692; http://dx.doi.org/10.1142/S0218126612500624
• 機構: Nanyang Technological University

This paper presents the design and implementation of a high resolution voltage-controlled oscillator (VCO)-based ΣΔADC for digital DC-DC converters. The proposed ADC adopts a robust VCO and a sixth-order delta-sigma modulation to attenuate the phase noise and output ripples. The delta-sigma modulation is realized using a cascade of a second-order high-pass filter and a fourth-order band-stop noise shaping filter. Chopper modulation is further employed to reduce the effect of 1/f noise. These have significantly increased the signal-to-noise+distortion ratio (SNDR) and lead to high linearity. The proposed ADC was designed and fabricated using CMOS 0.18 μm process. From measurement, the differential and integral nonlinearities of the ADC are determined to be ±0.5 LSB and ±0.65 LSB, respectively. The SNDR of the ADC is 49 dB up to 500 kHz, which gives an ENOB of 8 bits and quantization step of 2 mV. The ADC also features a low power consumption of 120 μA and a small IC area of 0.18 mm^2.