Van der Waals negative capacitance transistors

• Main Authors: Wang, Xiaowei, Yu, Peng, Lei, Zhendong, Zhu, Chao, Cao, Xun, Liu, Fucai, You, Lu, Zeng, Qingsheng, Deng, Ya, Zhou, Jiadong, Fu, Qundong, Wang, Junling, Huang, Yizhong, Liu, Zheng
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2019
• Subjects: Electronic Devices; Two-dimensional Materials; Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/107516; http://hdl.handle.net/10220/49725
• Institution: Nanyang Technological University

The Boltzmann distribution of electrons sets a fundamental barrier to lowering energy consumption in metal-oxide-semiconductor field-effect transistors (MOSFETs). Negative capacitance FET (NC-FET), as an emerging FET architecture, is promising to overcome this thermionic limit and build ultra-low-power consuming electronics. Here, we demonstrate steep-slope NC-FETs based on two-dimensional molybdenum disulfide and CuInP2S6 (CIPS) van der Waals (vdW) heterostructure. The vdW NC-FET provides an average subthreshold swing (SS) less than the Boltzmann’s limit for over seven decades of drain current, with a minimum SS of 28 mV dec−1. Negligible hysteresis is achieved in NC-FETs with the thickness of CIPS less than 20 nm. A voltage gain of 24 is measured for vdW NC-FET logic inverter. Flexible vdW NC-FET is further demonstrated with sub-60 mV dec−1 switching characteristics under the bending radius down to 3.8 mm. These results demonstrate the great potential of vdW NC-FET for ultra-low-power and flexible applications.