A 16-mW 1-GS/s with 49.6-dB SNDR TI-SAR ADC for software-defined radio in 65-nm CMOS

• Main Authors: Qiu, Lei, Tang, Kai, Zheng, Yuanjin, Siek, Liter, Zhu, Yan, U, Seng-Pan
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2019
• 主題: Engineering::Electrical and electronic engineering; Digital Background Calibration; Subradix-2
• 在線閱讀: https://hdl.handle.net/10356/107594; http://hdl.handle.net/10220/50344; http://dx.doi.org/10.1109/TVLSI.2017.2771811

This paper presents a 10-bit 1-GS/s four-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). To suppress the time skew, the full rate master clock-based sampling technique is adopted. The effect of sampling switch mismatches on time skew is addres...