I/O buffer model development from IBIS and IMIC for simulation in SPICE

I/O buffer model development from IBIS and IMIC for simulation in SPICE

In today's high-speed and high IC density digital system, many new problems have appeared. One significant issue is signal integrity (SI) which concerns signal purity. Signal noise and signal delay due to interconnect have been becoming to dominate circuit performance. In order to design reliab...

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書目詳細資料
主要作者:	Wang, Ying.
其他作者:	Tan, Han Ngee
格式:	Theses and Dissertations
語言:	English
出版:	2008
主題:	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits DRNTU::Engineering::Computer science and engineering::Computing methodologies::Simulation and modeling
在線閱讀:	http://hdl.handle.net/10356/13350
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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