A 10-bit 300 MS/s 5.8 mW SAR ADC with two-stage interpolation for PET imaging

A 10-bit 300 MS/s 5.8 mW SAR ADC with two-stage interpolation for PET imaging

In this paper, a high speed low power 2b/cycle successive approximation register (SAR) analog-To-digital converter (ADC) is proposed for medical imaging. The ADC adopts a two-stage differential pair based interpolation technique that can reduce resolution of the capacitive DAC and avoid usage of sma...

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Bibliographic Details
Main Authors: Qiu, Lei, Wang, Keping, Tang, Kai, Siek, Liter, Zheng, Yuanjin
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2020
Subjects:
Engineering::Electrical and electronic engineering
Interpolation
Medical Imaging
Online Access:https://hdl.handle.net/10356/137073
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Institution: Nanyang Technological University
Language: English
Description
Summary:In this paper, a high speed low power 2b/cycle successive approximation register (SAR) analog-To-digital converter (ADC) is proposed for medical imaging. The ADC adopts a two-stage differential pair based interpolation technique that can reduce resolution of the capacitive DAC and avoid usage of smaller unit capacitor. A meta-stability immunity technique is proposed to enhance the asynchronous conversion. A design example of 10-bit 2b/cycle SAR ADC with sampling rate up to 300 MS/s is fabricated. Dissipating 5.8 mW with 1.2 V supply and occupying an active area of 0.082 mm2, the measured SFDR and SNDR at Nyquist input are 59-dB and 51.5-dB respectively. It achieves an effective resolution bandwidth of 360 MHz and a figure-of-merit of 61fJ/conversion-step.

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