Investigation and design of low power circuit blocks for medical implant SOCs

• Main Author: Arjun, Ramaswami Palaniappan
• Other Authors: Siek Liter
• Format: Thesis-Doctor of Philosophy
• Language: English
• Published: Nanyang Technological University 2020
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/137142
• Institution: Nanyang Technological University

Biomedical implant devices are growing in recent years due to advancements in microelectronics, increase in chronic diseases and rising aging population. Since biomedical implants have stringent constraints on area and power consumption, majority of its electronic circuitry is realized using application specific system-on-chips (SoC). These SoCs contain various sub-blocks, intellectual property cores and standard cells in it for providing the intended functionality of the medical implant under consideration. In order to reduce the overall power and area consumption of the medical implant SoC, novel circuit architectures without compromise on performance for all individual SoC sub-blocks is necessary. This PhD research investigates 4 of the important sub-blocks of the medical implant SoC and proposes novel circuit architectures for these sub-blocks towards achieving a low power medical implant SoC without compromise on individual sub-block performance. Firstly, a novel ultra-low supply voltage and wide-input dynamic range flip-flop (FF) standard cell capable of operating at 0.16 V is designed in CMOS 40 nm. When compared with other FF topologies, the proposed capacitively boosted sense-amplifier FF topology achieves the least clock-to-output propagation delay and power-delay product. The proposed FF is also the only one capable of sampling low swing data signals from 0.2 V to 1 V. Thus, the proposed FF standard cell can be used to build the processor and logic unit of the implant SoC for achieving a better performance at ultra-low supply voltages. Secondly, a low power, low supply voltage and high time resolution time-to-digital converter (TDC) is designed and fabricated in 180 nm CMOS. While most of the current TDC architectures are designed to operate at a supply voltage of 1 V and above, the proposed TDC architecture utilizes capacitive boosting differential buffers for enabling the TDC to operate at a supply of 0.6 V even when using standard 1.8 V transistors in the design. The proposed TDC achieves a resolution of 1.74 ps and is suitable for use in the biosensor unit of implant SoC for time-of-flight measurements. Thirdly, a TDC-less low area all-digital phase locked loop (ADPLL) is designed and fabricated in 40 nm CMOS. Various circuit design techniques such as fractional capacitor tuning, capacitive boosting ring oscillator and frequency control mechanism is incorporated in the design to reduce silicon area and power consumption. The ADPLL operates at 0.68 V, covers the MedRadio frequency band, occupies a silicon area of 0.0186 mm2 and exhibits an rms jitter of 11.88 ps. The ADPLL is suitable for use in the transceiver unit of the implant SoC. Finally, negative skewed ring oscillators (NSRO) are analyzed and a sequence tree based time-domain approach that is able to determine the optimum oscillation behavior of an NSRO is proposed and validated using test chips fabricated in 180 nm CMOS. The scheme is also extended to differential ring oscillators. Such NSROs can be used in various applications inside the implant SoC, such as to design the TDC (ring oscillator based TDCs), VCO of PLL and pulse generators.